Since we're at it, we could start thinking about how to modify
the data path of the MC14500 design to run arithmetic.
I'm leaving out a few little details, like the XOR gate
needed to store the complement of RR to memory,
and the fact that not all instructions do modify
the Result Register (RR) and the Carry Flag (C).
We still have the Logic Unit (LU) from the MC14500,
but in order to build a full adder,
we have to send the output of the LU and the Carry Flag
through an XOR gate before writing the result into RR.
For logic instructions (and for some of the arithmetic instructions),
it's necessary to keep the Carry input at the XOR 0,
so we have to insert an AND gate.
Some of the arithmetic instructions might want to have the C Flag set,
like when processing the first Bit for a subtraction,
so we insert an OR gate into the output of the Carry Flag.
Like with our other ALU examples, the LU emits the propagate (P) signal,
which routes the Carry Flag from the previous Bit to the Carry of the next
Bit, when P is active.
For RR + mem, the LU is configurated as XOR.
For RR - mem, we calculate RR + /mem.
Inverting one input of a XOR gate is the same as inverting the output,
so the LU is configurated as XNOR when calculating RR - mem.
For some of the arithmetic instructions you might want to add 0 or 1 to RR.
Fortunately we already have the DIN Flag,
which is ANDed with the Bit from memory.
For loading a copy from the Carry Flag into the Result Register,
set the LU output to 0, and enable the Carry to pass through
the XOR into RR.
For loading a copy of RR into the Carry Flag, set the LU output to 0
and activate both AND gates for RR + mem, RR - mem...
so that RR is passed through, while the Bit from memory is ignored.
Of course, the processor would need to have more than 16 instructions,
and the instruction word wouldn't fit into 4 Bit anymore.
15 11 8 7 0 ------------------ |0000|Tttt|########| ------------------
An instruction word like that loads an 8 Bit literal value
into a timer (hey, it's just an example).
Except when Bit 11 is 0. Depending on Bit 8, the value
is loaded into the high or low Byte of a pointer,
which is selected by Bit 9 and Bit 10.
It's easy.
We might want to have the 16 Bits for all the counters
mapped into memory to be able to do some address calculation.
For instance:
0x10..0x1F = Pointer 1.
0x20..0x2F = Pointer 2.
0x30..0x3F = Pointer 3.
A memory read/write at 0x04..0x07 would read/write the
memory Bit selected by Pointer 1, for 0x08..0x0B it's Pointer 2,
0x0C..0x0F it's Pointer 3.
You sure noticed, that I'm suggesting to reserve 4 Bits per Pointer.
That's because we could tie the control signals for the counters/Pointers
to the address lines A0 and A1, to trigger things like
postincrement/predecrement.
The only thing we need is a "LOOP" instruction,
to run a set of instructions like
LD [A]+ ADC [B]+ STO [Q]+8 times when adding two Bytes in memory.
Maybe tied to "Flag 0" again...
The disadvantage of such a design is, that it might require
more transistors, logic gates, flipflops, whatever...
than just building a minimalistic 16 Bit CPU.
...do we really need
LD A SBC B STO QOr could we replace that with
LDC B ADC A STO Q
Hmm...
[HOME] [UP]/ [BACK] [1] [2] [3] [4] [5] [6] [7] [8] [NEXT]
(c) Dieter Mueller 2008
| 毛脚女婿是什么意思 | 宫腔积液是什么 | 铁棍山药和普通山药有什么区别 | 淡墨是什么意思 | 止汗药什么最好 |
| 梦见自己升职了是什么预兆 | 四海扬名是什么生肖 | 梦见杀人是什么意思 | dha中文叫什么 | 支气管炎能吃什么水果 |
| 射精是什么感觉 | 结甲是什么病 | 补血吃什么药最快最好 | 腰痛挂什么科 | 舌头上有黑点是什么原因 |
| 早上打喷嚏是什么预兆 | 手指头抽筋是什么原因 | pvr是什么意思 | 移植后屁多是什么原因 | 禾真念什么 |
| 身上没长什么就是干痒hcv7jop6ns2r.cn | 绞股蓝和什么搭配喝减肥hcv8jop1ns4r.cn | 胃烧心吃什么食物好hcv9jop5ns3r.cn | 查染色体的目的是什么hcv7jop7ns4r.cn | 天然气是什么味道hcv8jop2ns5r.cn |
| 华盖什么意思hcv9jop6ns5r.cn | 气血亏吃什么补的快hcv7jop6ns6r.cn | 鲫鱼不能和什么一起吃onlinewuye.com | 电灯泡什么意思1949doufunao.com | 马桶对着卫生间门有什么不好hcv9jop2ns8r.cn |
| 广基息肉是什么意思hcv7jop9ns8r.cn | 烟雾病是什么hcv9jop2ns9r.cn | 月经喝什么比较好hcv8jop0ns0r.cn | 吃葡萄皮有什么好处huizhijixie.com | 血糖高的人吃什么水果好hcv8jop9ns0r.cn |
| 梦见笑是什么意思hcv7jop6ns2r.cn | 排卵期在什么时候hcv8jop5ns1r.cn | 胸椎退行性变什么意思hcv9jop0ns2r.cn | 肠胃痉挛吃什么药hcv7jop7ns3r.cn | 水瓶座和什么座最配hcv8jop9ns4r.cn |